module Uart_bps
(
	clk_100,rst,bps_start,
	bps_flag
);

input		clk_100;
input		rst;
input		bps_start;
output		bps_flag;

reg	[9:0]	time_cnt;
reg	[9:0]	time_cnt_n;
reg				bps_flag;
reg				bps_flag_n;

parameter bps_para	=	10'd868;
parameter bps_para_2	=	9'd434;

always	@	(posedge clk_100	or	negedge	rst)
begin
	if(!rst)
		time_cnt	<=	13'b0;
	else
		time_cnt <= time_cnt_n;
end

always	@	(*)
begin
	if((time_cnt==bps_para)||(!bps_start))
		time_cnt_n	=	1'b0;
	else
		time_cnt_n	=	time_cnt	+	1'b1;
end

always	@	(posedge clk_100	or	negedge rst)
begin
	if(!rst)
		bps_flag	<=	1'b0;
	else
		bps_flag	<= bps_flag_n;
end

always	@	(*)
begin
	if(time_cnt ==	bps_para_2)
		bps_flag_n	= 1'b1;
	else
		bps_flag_n	= 1'b0;
end

endmodule

	


